1. Field of the Invention
The present invention relates generally to electrical circuits, and more particularly, to a method and apparatus for testing the operation of digital circuits.
2. Related Art
The speed of today's data processors, and the complex digital circuits they contain, make detecting and resolving circuit errors difficult. Unlike the ability of logic synthesis software tools to resolve logic errors, circuit errors due to circuit designs, manufacturing flaws, and the like are not easily solved.
A fault may cause an error in computing when a digital component, such as an AND gate or a flip-flop, assigns an improper binary value to a signal at an input, referred to as voltage threshold fault. For example, a "one" is assigned instead of a "zero" or vice versa. A digital circuit will recognize a "one" if the sampled signal is above a certain predefined threshold voltage level; in this case, the signal is said to be in a "high" state. Similarly, a "zero" will be recognized if the sampled signal voltage is less than a lower predetermined threshold voltage level; in this case, the signal is said to be in a "low" state. If the signal is in a voltage range lying between the high and low states, the signal is said to be in an "intermediate" state.
Besides voltage threshold faults, digital components also experience what is referred to as performance faults. A performance fault is a defect in digital component which causes it to exhibit a propagation delay in excess of the circuit design limits. Conventional circuit testers have been particularly unsuccessful in obtaining the necessary digital signal information to perform the proper diagnoses of a digital circuit having components which are experiencing performance-type faults.
Two conventional techniques used by circuit testers to gather digital signal information from the device under test (DUT) for fault determination and analysis are known as the window compare technique and edge compare technique.
A circuit tester utilizing the window compare technique determines whether a digital signal stays either above or below predetermined voltage threshold levels while the "window" is open. This is typically used to verify that the sampled digital signal remains valid for some nominal time duration marked by the points in time when the window opens and closes. The problem with the window compare technique is that it only determines whether a threshold crossing has occurred. It does not determine the point in time of this threshold crossing occurrence. Without this information, performance-type errors cannot be detected.
In contrast to the window compare technique, devices utilizing the edge compare technique sample the digital signal occurring at a test node of a DUT during a very brief period of time. The sampled digital signal data is used to characterize the information which occurs at the test node during the entire clock cycle in which the sampling occurred. The difficulty with this technique is that very little information is sampled for a particular test node per clock cycle. Another disadvantage of the edge compare technique is its inability to continually sample and store the digital signal state occurring at the test node for diagnosis of performance errors.
While the above conventional techniques have proven to be generally effective in the diagnosis of certain types of digital circuit problems, they have been particularly ineffective in detecting and gathering data necessary for the diagnosis of performance faults in a DUT. What is needed is a digital signal detector which samples and stores a sufficient amount of digital signal data for proper identification and analysis of performance faults in digital circuits and their components.